1. Field of the Invention
The present invention relates to an image processing apparatus and method.
2. Description of the Related Art
An image processing module generally has two types of interface, namely a CPU interface for setting a register and a data interface for inputting and outputting image data. In order for control to be performed by the CPU interface, such an image processing module requires execution of the following sequence:
notifying the CPU of end of image processing by an interrupt after a series of image processes ends; and
starting the next image processing operation after the setting of a register for the purpose of the next process.
Further, in a case where a change in the CPU is accompanied by a change in the CPU interface, the image processing module must be re-fabricated or the interface must be converted as by a wrapper.
In order to solve these problems, a method of putting data for setting a register and image data to be processed in the form of commands and transferring the commands on the same path has been proposed. The flow of processing according to this method will be described with reference to FIG. 1.
FIG. 1 is a block diagram of an image processor for executing a series of image processing operations. Shown in FIG. 1 are a CPU 701; DMACs 702, 706 for controlling DMA transfer; image processing modules 703 to 705 (modules A to C); a memory controller 707; and a memory 708. A gamma correction circuit and color conversion circuit, etc., can be mentioned as the image processing modules 703 to 705. “DMA” is the abbreviation of “Direct Memory Access”.
Before the start of image processing or in predetermined units of processing, the CPU 701 generates a register command for reading and writing from and to a register in each image processing module, or a data command containing pixel data.
FIGS. 2A and 2B illustrate specific examples of formats of these commands. As shown in FIG. 2A, the register command contains header information, a register address and a register set value. The header information includes a command identification bit, a module ID and a read/write identification bit. The command identification bit indicates whether the command is a register command or a data command. For example, the command is a register command if the command identification bit is “1” and is a data command, which is shown in FIG. 2B, if the command identification bit is “0”. The image processing modules determine whether the command type is the register command or data command by referring to the command identification bit. The module ID indicates in which image processing module the register command will be set. By referring to the module ID, the image processing module determines whether the received register command is for setting its own register. The read/write identification bit represents whether the register command is a read or write command. For example, the register command is register write (register write command) if the read/write identification bit is “1” and register read (register read command) if the read/write identification bit is “0”.
On the other hand, as illustrated in FIG. 2B, the header information of the data command includes a command identification bit having a value of “0” indicative of the data command, and an image control signal such as a data-start bit and a data-end bit. The CPU 701 stores the created command in memory 708.
Further, the CPU 701 also puts image data in the form of a command and stores it in the memory 708 as a data command. When a command in a prescribed unit of processing is stored in the memory 708, the CPU 701 sets an access address, which is for accessing the memory 708, in the registers of the DMACs 702 and 706 and starts operating.
The DMAC 702 reads in commands from the memory 708 successively and transfers the commands to image processing module A. In a case where the image processing module B (704) and image processing module C (705) have determined that an entered command is the register write command and, moreover, that the command is directed at itself as determined from the module ID, a register setting is performed. When the accepted command is the register read command, a value read from the target register indicated by the register address is set as the register set value of the read command and is transferred to the next image processing module. When the received command is the data command, processing is executed using this data, the result of processing is set in the data command and the command is transferred to the next image processing module. The DMAC 706 accepts the command that has been output from the image processing module C (705) and writes the command to the memory 708.
Thus, it is so arranged that setting of a register and data input can be set from the same port. This means that any sequence can be executed without a CPU interrupt. A further advantage is that even if there is a change in the CPU interface, no change whatsoever is required of the image processing modules.
Further, Japanese Patent Application Laid-Open No. 10-011388 describes a DMA control apparatus having a controller for generating transfer-source and transfer-destination addresses in order to lighten the CPU load.
However, in a case where it is so arranged that header information other than a register set value and addresses are stored in the memory 708, a large memory capacity and transmission band are required. As a consequence, needless memory capacity and transmission band are consumed. Further, in a case where it has been arranged to put image data in command form and store the command, the task of converting the image data to a command is required of the CPU 701 and the load on the CPU is increased. Furthermore, the task relating to the conversion to a command is not overcome even if the DMA control apparatus of Japanese Patent Application Laid-Open No. 10-011388 is applied.